Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
This paper presents a pinpoint test set relaxation method for test compression that maximally derives the capability of a run-length encoding technique such as Golomb coding or fr...
Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Cha...
—We present a dictionary-based test data compression approach for reducing test data volume and testing time in SOCs. The proposed method is based on the use of a small number of...