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DFT
2006
IEEE
148views VLSI» more  DFT 2006»
13 years 7 months ago
Bilateral Testing of Nano-scale Fault-tolerant Circuits
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. ...
Lei Fang, Michael S. Hsiao
EAAI
2007
103views more  EAAI 2007»
13 years 5 months ago
Particle swarm-based optimal partitioning algorithm for combinational CMOS circuits
This paper presents a swarm intelligence based approach to optimally partition combinational CMOS circuits for pseudoexhaustive testing. The partitioning algorithm ensures reducti...
Ganesh K. Venayagamoorthy, Scott C. Smith, Gaurav ...
JAIR
2010
165views more  JAIR 2010»
13 years 3 months ago
A Model-Based Active Testing Approach to Sequential Diagnosis
Model-based diagnostic reasoning often leads to a large number of diagnostic hypotheses. The set of diagnoses can be reduced by taking into account extra observations (passive mon...
Alexander Feldman, Gregory M. Provan, Arjan J. C. ...
DAC
2006
ACM
14 years 6 months ago
MARS-C: modeling and reduction of soft errors in combinational circuits
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we pre...
Natasa Miskov-Zivanov, Diana Marculescu
DAC
2006
ACM
14 years 6 months ago
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty
Existing approaches to timing analysis under uncertainty are based on restrictive assumptions. Statistical STA techniques assume that the full probabilistic distribution of parame...
Wei-Shen Wang, Vladik Kreinovich, Michael Orshansk...