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ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
In this paper, an algorithm for the coupled simulation of circuit and piezoelectric laminate devices is presented. A finite element solver for piezoelectric laminates is included ...
ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
With continuing scaling of CMOS process, process variations in the form of die-to-die and within-die variations become significant which cause timing uncertainty. This paper prop...
ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
We present a silicon-on-insulator (SOI) pass-transistor logic (PTL) gate with an active body bias control circuit and compare the proposed PTL gate with other types of PTL gates w...
ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
In this paper, we propose a new physical synthesis methodology, PDL, which relaxes the timing constraints to obtain best optimality in terms of layout quality and timing quality. ...
ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
Inductance associated with on-chip wires can no longer be ignored as chip operation frequencies increase into GHz regime. Because the magnetic field propagates a very long range, ...