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ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
Precise chip-level timing requires careful modeling of the interaction between logic drivers and interconnect. Existing static-timing analysis methodologies generate models for dr...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
As technology feature size is reduced, ESD becomes one of the dominant failure modes due to the lower gate oxide breakdown voltage. Also, the holding voltage of LVTSCR devices is ...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
Limited Switch Dynamic Logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primar...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper proposes an efficient automation platform that provides fast and reliable path to analog circuit design for desired specifications. Circuit heuristics and hierarchy a...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
— Multiple power supply voltages are often used in modern high performance ICs such as microprocessors to decrease power consumption without affecting circuit speed. The system o...