Controlled-Load Limited Switch Dynamic Logic Circuit

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Limited Switch Dynamic Logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primarily due to the reduction of capacitance on the clock network. The controlled-load LSDL is shown to be more robust to noise and power rail bounces. A 64-bit rotator circuit was used in the analysis. The effect of process variation on circuit performance is also evaluated.

Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Now

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64-bit Rotator Circuit | Hardware | ISQED 2005 | Performance Logic Circuit | Switch Dynamic Logic |

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Added	25 Jun 2010
Updated	25 Jun 2010
Type	Conference
Year	2005
Where	ISQED
Authors	Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown

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Controlled-Load Limited Switch Dynamic Logic Circuit

64-bit Rotator Circuit | Hardware | ISQED 2005 | Performance Logic Circuit | Switch Dynamic Logic |

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