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ISQED
2006
IEEE
176views Hardware» more  ISQED 2006»
13 years 10 months ago
Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages
— A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power...
Zhiyu Liu, Volkan Kursun
ISQED
2006
IEEE
118views Hardware» more  ISQED 2006»
13 years 10 months ago
Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices
This paper presents a unique SEU (single Event Upset) mitigation technique based upon Temporal Data Sampling for synchronous circuits and configuration bit storage for programmabl...
Sajid Baloch, Tughrul Arslan, Adrian Stoica
ISQED
2006
IEEE
153views Hardware» more  ISQED 2006»
13 years 10 months ago
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two...
Chong Zhao, Sujit Dey
ISQED
2006
IEEE
106views Hardware» more  ISQED 2006»
13 years 10 months ago
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circui...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...
ISQED
2006
IEEE
94views Hardware» more  ISQED 2006»
13 years 10 months ago
System-Level SRAM Yield Enhancement
It is well known that SRAM constitutes a large portion of modern integrated circuits, with 80% or more of the total transistors being dedicated to SRAM in a typical processor or S...
Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park...