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ISQED
2006
IEEE
126views Hardware» more  ISQED 2006»
9 years 11 months ago
Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity
The increase in packing density has led to a higher power density in the chip which in turn has led to an increase in temperature on the chip. Temperature affects reliability, per...
Anand Ramalingam, David Z. Pan, Frank Liu, Sani R....
ISQED
2006
IEEE
124views Hardware» more  ISQED 2006»
9 years 11 months ago
DFM Metrics for Standard Cells
Design for Manufacturability (DFM) is becoming increasingly important as process geometries shrink. Conventional design rule pass/fail is not adequate to quantify DFM compliance. ...
Robert C. Aitken
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
9 years 11 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
ISQED
2006
IEEE
89views Hardware» more  ISQED 2006»
9 years 11 months ago
Study of Floating Fill Impact on Interconnect Capacitance
It is well known that fill insertion adversely affects total and coupling capacitance of interconnects. While grounded fill can be extracted by full-chip extractors, floating ...
Andrew B. Kahng, Kambiz Samadi, Puneet Sharma
ISQED
2006
IEEE
147views Hardware» more  ISQED 2006»
9 years 11 months ago
Compact Reduced Order Modeling for Multiple-Port Interconnects
— In this paper, we propose an efficient model order reduction (MOR) algorithm, called MTermMOR, for modeling interconnect circuits with large number of external ports. The prop...
Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng ...
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