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ISQED
2010
IEEE
127views Hardware» more  ISQED 2010»
13 years 3 months ago
Limits of bias based assist methods in nano-scale 6T SRAM
Reduced device dimensions and operating voltages that accompany technology scaling have led to increased design challenges with each successive technology node. Large scale 6T SRA...
Randy W. Mann, Satyanand Nalam, Jiajing Wang, Bent...
ISQED
2010
IEEE
176views Hardware» more  ISQED 2010»
13 years 3 months ago
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead
Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and communication applications realized using system on...
Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dh...
ISQED
2010
IEEE
114views Hardware» more  ISQED 2010»
13 years 11 months ago
Toward effective utilization of timing exceptions in design optimization
— Timing exceptions in IC implementation processes, especially timing verification, help reduce pessimism that arises from unnecessary timing constraints by masking non-function...
Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang
ISQED
2010
IEEE
141views Hardware» more  ISQED 2010»
13 years 11 months ago
Assessing chip-level impact of double patterning lithography
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...