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ISSS
1998
IEEE
103views Hardware» more  ISSS 1998»
13 years 9 months ago
False Path Analysis Based on a Hierarchical Control Representation
False path analysis is an activity with applications in a variety of computer science and engineering domains like for instance high-level synthesis, worst case execution time est...
Apostolos A. Kountouris, Christophe Wolinski
ISSS
1998
IEEE
129views Hardware» more  ISSS 1998»
13 years 9 months ago
Application-Specific Heterogeneous Multiprocessor Synthesis Using Differential-Evolution
This paper presents an application-specific, heterogeneous multiprocessor synthesis system, named HeMPS, that combines a form of Evolutionary Computation known as Differential Evo...
Allan Rae, Sri Parameswaran
ISSS
1998
IEEE
152views Hardware» more  ISSS 1998»
13 years 9 months ago
Code Generation for Compiled Bit-True Simulation of DSP Applications
Bit-true simulation veri es the nite word length choices in the VLSI implementation of a DSP application. Present-day bit-true simulation tools are time consuming. We elaborate a ...
Luc De Coster, Marleen Adé, Rudy Lauwereins...
ISSS
1998
IEEE
73views Hardware» more  ISSS 1998»
13 years 9 months ago
Resource Constrained Modulo Scheduling with Global Resource Sharing
Commonly used scheduling algorithms in high-level synthesis are not capable of sharing resources across process boundaries. This results in the usage of at least one resource per ...
Christoph Jäschke, Rainer Laur
ISSS
1998
IEEE
117views Hardware» more  ISSS 1998»
13 years 9 months ago
HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation
The concept of retargetability enables compiler technology to keep pace with the increasing variety of domain-speci c embedded processors. In order to achieve user retargetability,...
Rainer Leupers