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ISSS
2000
IEEE
129views Hardware» more  ISSS 2000»
13 years 9 months ago
IP Reuse in the System on a Chip Era
Intellectual Property (IP) Reuse is one of the keys for System on a Chip (SoC) design productivity improvement. Although IP reuse has been explored both technically and as a busin...
Warren Savage, John Chilton, Raul Camposano
ISSS
2000
IEEE
155views Hardware» more  ISSS 2000»
13 years 9 months ago
Intervals in Software Execution Cost Analysis
Timing and power consumption of embedded systems are state and input data dependent. Formal analysis of such dependencies leads to intervals rather than single values. These inter...
Fabian Wolf, Rolf Ernst
ISSS
2000
IEEE
191views Hardware» more  ISSS 2000»
13 years 8 months ago
Conditional Scheduling for Embedded Systems using Genetic List Scheduling
One important part of a HW/SW codesign system is the scheduler which is needed in order to determine if a given HW/SW partitioning is suitable for a given application. In this pap...
Martin Grajcar
ISSS
2000
IEEE
94views Hardware» more  ISSS 2000»
13 years 9 months ago
A Transformational Approach to Constraint Relaxation of a Time-driven Simulation Model
Time-driven simulation models typically model timing in an idealized way that is over-constrained and cannot be directly implemented. In this paper we present a transformation to ...
Marek Jersak, Ying Cai, Dirk Ziegenbein, Rolf Erns...
ISSS
2000
IEEE
109views Hardware» more  ISSS 2000»
13 years 8 months ago
FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors
The paper presents a novel software-pipelining algorithm suitable for optimizing compilers targeting embedded VLIW processors. The proposed algorithm is different from previous ap...
Cagdas Akturan, Margarida F. Jacome