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ISSS
2000
IEEE
127views Hardware» more  ISSS 2000»
13 years 9 months ago
Lower Bound Estimation for Low Power High-Level Synthesis
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Sta...
ISSS
2000
IEEE
88views Hardware» more  ISSS 2000»
13 years 9 months ago
Experiments with the Peripheral Virtual Component Interface
The Peripheral Virtual Component Interface, or PVCI, is a standard intended to simplify the interfacing of peripheral cores to on-chip buses in a system-on-a-chip, by standardizin...
Roman L. Lysecky, Frank Vahid, Tony Givargis
ISSS
2000
IEEE
91views Hardware» more  ISSS 2000»
13 years 9 months ago
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
Tony Givargis, Frank Vahid, Jörg Henkel
ISSS
2000
IEEE
127views Hardware» more  ISSS 2000»
13 years 8 months ago
Low Power Storage Cycle Budget Distribution Tool Support for Hierarchical Graphs
In data dominated applications, like multi-media and telecom applications, data storage and transfers are the most important factors in terms of energy consumption, area and syste...
Erik Brockmeyer, Arnout Vandecappelle, Sven Wuytac...
CODES
2006
IEEE
13 years 10 months ago
A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation
Traditionally, instruction-set simulators (ISS’s) are sequential programs running on individual processors. Besides the advances of simulation techniques, ISS’s have been main...
Wei Qin, Joseph D'Errico, Xinping Zhu