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ITC
2002
IEEE
13 years 10 months ago
2002
IEEE
ITC
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper develops a novel approach for formally verifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped int...
ITC
2002
IEEE
13 years 10 months ago
2002
IEEE
Conventional fault simulation techniques for FPGAs are very complicated and time consuming. The other alternative, FPGA fault emulation technique, is incomplete, and can be used o...
ITC
2002
IEEE
13 years 10 months ago
2002
IEEE
1 This paper presents a test input data compression technique, which can be used to reduce input test data volume, test time, and the number of required tester channels. The techni...
ITC
2002
IEEE
13 years 10 months ago
2002
IEEE
ct Characterizing board test coverage as a percentage of devices or nodes having tests does not accurately portray coverage, especially in a limited access testing environment that...