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    PPL
    2008
    96views more  PPL 2008»
    A Hybrid Shared Memory Execution Model for a Data Parallel Language with I/O
    13 years 5 months ago
    A Hybrid Shared Memory Execution Model for a Data Parallel Language with I/O
    Download  www.sac-home.org
    Execution of programs with data parallel language constructs is either based on the fork/join or on the SPMD model. Whereas the former executes a program sequentially and confines...
    Clemens Grelck, Steffen Kuthe, Sven-Bodo Scholz
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    PPL
    2008
    144views more  PPL 2008»
    Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs
    13 years 5 months ago
    Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs
    Download  ce.et.tudelft.nl
    This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronizati...
    Konstantinos Tatas, Costas Kyriacou, Paraskevas Ev...
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    PPL
    2008
    264views more  PPL 2008»
    A Performance Evaluation of the Nehalem Quad-Core Processor for Scientific Computing
    13 years 5 months ago
    A Performance Evaluation of the Nehalem Quad-Core Processor for Scientific Computing
    Download  www.ccs3.lanl.gov
    In this work we present an initial performance evaluation of Intel's latest, secondgeneration quad-core processor, Nehalem, and provide a comparison to first-generation AMD a...
    Kevin J. Barker, Kei Davis, Adolfy Hoisie, Darren ...
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    BMCBI
    2008
    111views more  BMCBI 2008»
    MLIP: using multiple processors to compute the posterior probability of linkage
    13 years 5 months ago
    MLIP: using multiple processors to compute the posterior probability of linkage
    Download  www.biomedcentral.com
    Background: Localization of complex traits by genetic linkage analysis may involve exploration of a vast multidimensional parameter space. The posterior probability of linkage (PP...
    Manika Govil, Alberto Maria Segre, Veronica J. Vie...
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    PPL
    2008
    185views more  PPL 2008»
    On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
    13 years 5 months ago
    On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
    Download  gram.eng.uci.edu
    As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
    Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
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