Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs

This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronization Unit (TSU) on FPGA, a hardware unit that enables thread execution using dataflow-like scheduling policy on a chip multiprocessor. Threads are scheduled for execution based on data availability, i.e., a thread is scheduled for execution only if its input data is available. This model of execution is called the Data-Driven Multithreading (DDM) model of execution. The DDM model has been evaluated using an execution driven simulator. To validate the simulation results, a 2-node DDM chip multiprocessor has been implemented on a Xilinx Virtex-II Pro FPGA with two PowerPC processors hardwired on the FPGA. Measurements on the hardware prototype show that the TSU can be implemented with a moderate hardware budget. The 2-node multiprocessor has been implemented with less than half of the reconfigurable hardware avai...

• Type: Journal
• Year: 2008
• Where: PPL
• Authors: Konstantinos Tatas, Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso, Stephan Wong
• Keywords: Chip Multiprocessor, FPGA, PPL 2008, Virtex-II Pro FPGA