Sciweavers

12 search results - page 2 / 3
» vlsid 1997
Sort
View
VLSID
1997
IEEE
106views VLSI» more  VLSID 1997»
13 years 9 months ago
Low-Power Configurable Processor Array for DLMS Adaptive Filtering
I n this paper, we first present a pipelined delayed least mean square (DLMS) adaptive filter architecture whose power dissipation meets a specified budget. This low-power archite...
S. Ramanathan, V. Visvanathan
VLSID
1997
IEEE
109views VLSI» more  VLSID 1997»
13 years 9 months ago
Delay-Insensitive Carry-Lookahead Adders
Integer addition is one of the most important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their adde...
Fu-Chiung Cheng, Stephen H. Unger, Michael Theobal...
VLSID
1997
IEEE
112views VLSI» more  VLSID 1997»
13 years 9 months ago
Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs
An exclusive-OR transform of input variables significantly reduces the size of the PLA implementation for adder and comparator circuits. For n bit adder circuits, the size of PLA ...
James Jacob, P. Srinivas Sivakumar, Vishwani D. Ag...
VLSID
1997
IEEE
98views VLSI» more  VLSID 1997»
13 years 9 months ago
Synthesis for Logical Initializability of Synchronous Finite State Machines
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
Montek Singh, Steven M. Nowick
VLSID
1997
IEEE
399views VLSI» more  VLSID 1997»
13 years 9 months ago
A Self-Biased High Performance Folded Cascode CMOS Op-Amp
Cascode CMOS op-amps use a large number of external bias voltages. This results in numerous drawbacks, namely, an area and power overhead, susceptiblity of the bias lines to noise...
Pradip Mandal, V. Visvanathan