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VTS
2003
IEEE
95views Hardware» more  VTS 2003»
13 years 10 months ago
Testing SoC Interconnects for Signal Integrity Using Boundary Scan
As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-o...
Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nour...
VTS
2003
IEEE
87views Hardware» more  VTS 2003»
13 years 10 months ago
An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits
We present a novel analog checker that adjusts dynamically the error threshold to the magnitude of its input signals. We demonstrate that this property is crucial for accurate con...
Haralampos-G. D. Stratigopoulos, Yiorgos Makris
VTS
2003
IEEE
127views Hardware» more  VTS 2003»
13 years 10 months ago
Bist Reseeding with very few Seeds
Reseeding is used to improve fault coverage of pseudorandom testing. The seed corresponds to the initial state of the LFSR before filling the scan chain. The number of determinist...
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McC...
VTS
2003
IEEE
88views Hardware» more  VTS 2003»
13 years 10 months ago
Use of Multiple IDDQ Test Metrics for Outlier Identification
With increasing circuit complexity and reliability requirements, screening outlier chips is an increasingly important test challenge. This is especially true for IDDQ test due to ...
Sagar S. Sabade, D. M. H. Walker
VTS
2003
IEEE
122views Hardware» more  VTS 2003»
13 years 10 months ago
A Reconfigurable Shared Scan-in Architecture
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
Samitha Samaranayake, Emil Gizdarski, Nodari Sitch...