Use of Multiple IDDQ Test Metrics for Outlier Identification

With increasing circuit complexity and reliability requirements, screening outlier chips is an increasingly important test challenge. This is especially true for IDDQ test due to increased spread in the distribution. In this paper, the concept of current ratio is extended to exploit waferlevel spatial correlation. Two metrics – current ratio and neighbor current ratio – are combined to screen outliers at the wafer level. We demonstrate that a single metric alone cannot screen all outliers, however, their combination can be used for effectively screening outlier chips. Analyses based on industrial test data are presented.

• Type: Conference
• Year: 2003
• Where: VTS
• Authors: Sagar S. Sabade, D. M. H. Walker
• Keywords: Current Ratio, Important Test Challenge, Outlier Chips, VTS 2003