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VTS
2003
IEEE
131views Hardware» more  VTS 2003»
14 years 4 months ago
Efficient Implication - Based Untestable Bridge Fault Identifier
: This paper presents a novel, low cost technique based on implications to identify untestable bridging faults in sequential circuits. Sequential symbolic simulation [1] is first p...
Manan Syal, Michael S. Hsiao, Kiran B. Doreswamy, ...
VTS
2003
IEEE
89views Hardware» more  VTS 2003»
14 years 4 months ago
Diagnosis of Delay Defects Using Statistical Timing Models
— In this paper, we study the problem of delay defect diagnosis based on statistical timing models. We propose a diagnosis algorithm that can effectively utilize statistical timi...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-...
VTS
2003
IEEE
119views Hardware» more  VTS 2003»
14 years 4 months ago
A Circuit Level Fault Model for Resistive Opens and Bridges
Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are...
Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. ...
VTS
2003
IEEE
119views Hardware» more  VTS 2003»
14 years 4 months ago
Test Data Compression Using Dictionaries with Fixed-Length Indices
—We present a dictionary-based test data compression approach for reducing test data volume and testing time in SOCs. The proposed method is based on the use of a small number of...
Lei Li, Krishnendu Chakrabarty
VTS
2003
IEEE
115views Hardware» more  VTS 2003»
14 years 4 months ago
Fault Testing for Reversible Circuits
Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today’s VLSI circuits, if curre...
Ketan N. Patel, John P. Hayes, Igor L. Markov