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VTS
2007
IEEE
95views Hardware» more  VTS 2007»
14 years 1 days ago
Delay Test Quality Evaluation Using Bounded Gate Delays
: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...
Soumitra Bose, Vishwani D. Agrawal
VTS
2007
IEEE
203views Hardware» more  VTS 2007»
14 years 1 days ago
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code
Conventional error correcting code (ECC) schemes used in memories and caches cannot correct double bit errors caused by a single event upset (SEU). As memory density increases, mu...
Avijit Dutta, Nur A. Touba
VTS
2007
IEEE
129views Hardware» more  VTS 2007»
14 years 1 days ago
Supply Voltage Noise Aware ATPG for Transition Delay Faults
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
VTS
2007
IEEE
79views Hardware» more  VTS 2007»
14 years 1 days ago
Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression
A methodology is presented for improving the amount of compression achieved by continuous-flow decompressors by using multiple ratios of scan chains to tester channels (i.e., expa...
Richard Putman, Nur A. Touba
VTS
2007
IEEE
143views Hardware» more  VTS 2007»
14 years 1 days ago
RTL Test Point Insertion to Reduce Delay Test Volume
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
Kedarnath J. Balakrishnan, Lei Fang