: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...
Conventional error correcting code (ECC) schemes used in memories and caches cannot correct double bit errors caused by a single event upset (SEU). As memory density increases, mu...
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
A methodology is presented for improving the amount of compression achieved by continuous-flow decompressors by using multiple ratios of scan chains to tester channels (i.e., expa...
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...