Sciweavers

Share
warning: Creating default object from empty value in /var/www/modules/taxonomy/taxonomy.module on line 1416.
FPGA
2009
ACM
168views FPGA» more  FPGA 2009»
11 years 4 months ago
Large-scale wire-speed packet classification on FPGAs
Multi-field packet classification is a key enabling function of a variety of network applications, such as firewall processing, Quality of Service differentiation, traffic billing...
Weirong Jiang, Viktor K. Prasanna
ANCS
2009
ACM
11 years 4 months ago
Divide and discriminate: algorithm for deterministic and fast hash lookups
Exact and approximate membership lookups are among the most widely used primitives in a number of network applications. Hash tables are commonly used to implement these primitive ...
Domenico Ficara, Stefano Giordano, Sailesh Kumar, ...
JSAC
2006
163views more  JSAC 2006»
11 years 6 months ago
Fast and Scalable Pattern Matching for Network Intrusion Detection Systems
High-speed packet content inspection and filtering devices rely on a fast multi-pattern matching algorithm which is used to detect predefined keywords or signatures in the packets....
Sarang Dharmapurikar, John W. Lockwood
GLOBECOM
2008
IEEE
11 years 6 months ago
Highly Memory-Efficient LogLog Hash for Deep Packet Inspection
As the network line rates reach 40 Gbps today and 100 Gbps in the near future, performing deep packet inspection (DPI) in the Network Intrusion Detection and Prevention Systems (NI...
Masanori Bando, N. Sertac Artan, H. Jonathan Chao
ISLPED
2010
ACM
229views Hardware» more  ISLPED 2010»
11 years 6 months ago
An energy efficient cache design using spin torque transfer (STT) RAM
The on-chip memory is a dominant source of power and energy consumption in modern and future processors. This paper explores the use of a new emerging non-volatile memory technolo...
Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatte...
DATE
2005
IEEE
138views Hardware» more  DATE 2005»
11 years 8 months ago
BB-GC: Basic-Block Level Garbage Collection
Memory space limitation is a serious problem for many embedded systems from diverse application domains. While circuit/packaging techniques are definitely important to squeeze la...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin
HOTOS
2009
IEEE
11 years 10 months ago
Reinventing Scheduling for Multicore Systems
High performance on multicore processors requires that schedulers be reinvented. Traditional schedulers focus on keeping execution units busy by assigning each core a thread to ru...
Silas Boyd-Wickizer, Robert Morris, M. Frans Kaash...
DATE
2010
IEEE
113views Hardware» more  DATE 2010»
11 years 11 months ago
PM-COSYN: PE and memory co-synthesis for MPSoCs
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang
ASPDAC
2004
ACM
106views Hardware» more  ASPDAC 2004»
12 years 1 hour ago
A novel memory size model for variable-mapping in system level design
— It is predicted that 70% of the chip area will be occupied by memories in future system-onchips. The minimization of on-chip memory hence becomes increasingly important for cos...
Lukai Cai, Haobo Yu, Daniel Gajski
ISCA
2007
IEEE
126views Hardware» more  ISCA 2007»
12 years 26 days ago
Comparing memory systems for chip multiprocessors
There are two basic models for the on-chip memory in CMP systems: hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison o...
Jacob Leverich, Hideho Arakida, Alex Solomatnikov,...
books