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    DAC
    2005
    ACM
    148views Computer Architecture» more  DAC 2005»
    Smart diagnostics for configurable processor verification
    13 years 6 months ago
    Smart diagnostics for configurable processor verification
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    This paper describes a novel technique called Embedded Test-bench Control (ETC), extensively used in the verification of Tensilica’s latest configurable processor. Conventional ...
    Sadik Ezer, Scott Johnson
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    DAC
    2005
    ACM
    141views Computer Architecture» more  DAC 2005»
    A combined feasibility and performance macromodel for analog circuits
    13 years 6 months ago
    A combined feasibility and performance macromodel for analog circuits
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    The need to reuse the performance macromodels of an analog circuit topology challenges existing regression based modeling techniques. A model of good reusability should have a num...
    Mengmeng Ding, Ranga Vemuri
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    DAC
    2005
    ACM
    139views Computer Architecture» more  DAC 2005»
    How accurately can we model timing in a placement engine?
    13 years 6 months ago
    How accurately can we model timing in a placement engine?
    Download  www.cecs.uci.edu
    This paper presents a novel placement algorithm for timing optimization based on a new and powerful concept, which we term differential timing analysis. Recognizing that accurate ...
    Amit Chowdhary, Karthik Rajagopal, Satish Venkates...
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    DAC
    2005
    ACM
    95views Computer Architecture» more  DAC 2005»
    A pattern matching coprocessor for network security
    13 years 6 months ago
    A pattern matching coprocessor for network security
    Download  www.cecs.uci.edu
    Young H. Cho, William H. Mangione-Smith
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    DAC
    2005
    ACM
    97views Computer Architecture» more  DAC 2005»
    Closing the power gap between ASIC and custom: an ASIC perspective
    13 years 6 months ago
    Closing the power gap between ASIC and custom: an ASIC perspective
    Download  videos.dac.com
    We investigate differences in power between application-specific integrated circuits (ASICs) and custom integrated circuits, with examples from 0.6um to 0.13um CMOS. A variety of ...
    David G. Chinnery, Kurt Keutzer
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    DAC
    2005
    ACM
    106views Computer Architecture» more  DAC 2005»
    Design methodology for wireless nodes with printed antennas
    13 years 6 months ago
    Design methodology for wireless nodes with printed antennas
    Download  www.cecs.uci.edu
    Jean-Samuel Chenard, Chun Yiu Chu, Zeljko Zilic, M...
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    DAC
    2005
    ACM
    93views Computer Architecture» more  DAC 2005»
    Streamline verification process with formal property verification to meet highly compressed design cycle
    13 years 6 months ago
    Streamline verification process with formal property verification to meet highly compressed design cycle
    Download  videos.dac.com
    Prosenjit Chatterjee
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    DAC
    2005
    ACM
    140views Computer Architecture» more  DAC 2005»
    Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
    13 years 6 months ago
    Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
    Download  www.cecs.uci.edu
    Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
    Hongliang Chang, Vladimir Zolotov, Sambasivan Nara...
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    DAC
    2005
    ACM
    108views Computer Architecture» more  DAC 2005»
    Explaining the gap between ASIC and custom power: a custom perspective
    13 years 6 months ago
    Explaining the gap between ASIC and custom power: a custom perspective
    Download  www.cecs.uci.edu
    Andrew Chang, William J. Dally
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    DAC
    2005
    ACM
    151views Computer Architecture» more  DAC 2005»
    Mapping statistical process variations toward circuit performance variability: an analytical modeling approach
    13 years 6 months ago
    Mapping statistical process variations toward circuit performance variability: an analytical modeling approach
    Download  www.cs.york.ac.uk
    A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...
    Yu Cao, Lawrence T. Clark
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