Sciweavers

CGO
2006
IEEE
13 years 10 months ago
Constructing Virtual Architectures on a Tiled Processor
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
David Wentzlaff, Anant Agarwal
VAMOS
2007
Springer
13 years 10 months ago
Adding Aspects to xADL 2.0 for Software Product Line Architectures
The Feature–Oriented approach provides a way of modelling commonalities and variabilities among products of a software product line. A feature model can be used as input for gen...
Lidia Fuentes, Nadia Gámez
ICCS
2007
Springer
13 years 10 months ago
Trikonic Inter-Enterprise Architectonic
There is a need for information, application, and other enterprise architectures which are robust and flexible enough to meet the challenges of today’s heterogeneous, rapidly cha...
Gary Richmond
CHES
2007
Springer
154views Cryptology» more  CHES 2007»
13 years 10 months ago
Multi-gigabit GCM-AES Architecture Optimized for FPGAs
Abstract. This paper presents a design-space exploration of the Galois/Counter Mode (GCM) algorithm with Advanced Encryption Standard (AES) as underlying block cipher for high thro...
Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert ...
ISPASS
2007
IEEE
13 years 10 months ago
Cross Binary Simulation Points
Architectures are usually compared by running the same workload on each architecture and comparing performance. When a single compiled binary of a program is executed on many diff...
Erez Perelman, Jeremy Lau, Harish Patil, Aamer Jal...
ISCAS
2007
IEEE
99views Hardware» more  ISCAS 2007»
13 years 10 months ago
A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints
— Hermitian Codes offer desirable properties such as large code lengths, good error-correction at high code rates, etc. The main problem in making Hermitian codes practical is to...
Rachit Agarwal, Emanuel M. Popovici, Brendan O'Fly...
SASP
2008
IEEE
94views Hardware» more  SASP 2008»
13 years 11 months ago
An MDCT Hardware Accelerator for MP3 Audio
— With the increasing popularity of MP3 audio, there is a need to develop cost and power efficient architectures for the MP3 encoder and decoder. This paper describes dedicated ...
Xingdong Dai, Meghanad D. Wagh
DSD
2008
IEEE
95views Hardware» more  DSD 2008»
13 years 11 months ago
Programmable Numerical Function Generators for Two-Variable Functions
This paper proposes a design method and programmable architectures for numerical function generators (NFGs) of two-variable functions. To realize a two-variable function in hardwa...
Shinobu Nagayama, Jon T. Butler, Tsutomu Sasao
CDC
2008
IEEE
128views Control Systems» more  CDC 2008»
13 years 11 months ago
Time-robust discrete control over networked Loosely Time-Triggered Architectures
In this paper we consider Loosely Time-Triggered Architectures (LTTA) as a networked infrastructure for deploying discrete control. LTTA are distributed architectures in which 1/ ...
Paul Caspi, Albert Benveniste
DSD
2009
IEEE
124views Hardware» more  DSD 2009»
13 years 11 months ago
Network-on-Chip Architecture Exploration Framework
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The au...
Timo Schönwald, Jochen Zimmermann, Oliver Bri...