Sciweavers

ASAP
2006
IEEE
138views Hardware» more  ASAP 2006»
13 years 9 months ago
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...
Marjan Karkooti, Predrag Radosavljevic, Joseph R. ...
ASAP
2006
IEEE
108views Hardware» more  ASAP 2006»
13 years 9 months ago
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding
State-of-the-art communication standards make extensive use of Turbo codes. The complex and power consuming designs that currently implement the turbo decoder expose the need for ...
Pablo Ituero, Marisa López-Vallejo
ASAP
2006
IEEE
168views Hardware» more  ASAP 2006»
13 years 9 months ago
Dual-Processor Design of Energy Efficient Fault-Tolerant System
A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the completion of the prim...
Shaoxiong Hua, Pushkin R. Pari, Gang Qu
ASAP
2006
IEEE
121views Hardware» more  ASAP 2006»
13 years 9 months ago
Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit
In this paper, we propose a reconfigurable hardware accelerator for fixed-point-matrix-vector-multiply/add operations, capable to work on dense and sparse matrices formats. The pr...
Humberto Calderon, Stamatis Vassiliadis
ASAP
2006
IEEE
162views Hardware» more  ASAP 2006»
13 years 9 months ago
Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts
Parameterized static affine nested loop programs can be automatically converted to input-output equivalent Kahn Process Network specifications. These networks turn out to be close...
Ed F. Deprettere, Todor Stefanov, Shuvra S. Bhatta...
ASAP
2006
IEEE
89views Hardware» more  ASAP 2006»
13 years 9 months ago
Polyhedral Modeling and Analysis of Memory Access Profiles
In this paper, we propose to model memory access profile information as loop nests exhibiting useful characteristics on the memory behavior, such as periodicity, linearly linked m...
Philippe Clauss, Bénédicte Kenmei
ASAP
2006
IEEE
145views Hardware» more  ASAP 2006»
13 years 11 months ago
2D-VLIW: An Architecture Based on the Geometry of Computation
This work proposes a new architecture and execution model called 2D-VLIW. This architecture adopts an execution model based on large pieces of computation running over a matrix of...
Ricardo Santos, Rodolfo Azevedo, Guido Araujo
ASAP
2006
IEEE
97views Hardware» more  ASAP 2006»
13 years 11 months ago
Dynamic-SIMD for lens distortion compensation
An increasing computational demand is placed on the image processing capacity of current and future smart cameras. SIMD processor architectures provide an efficient solution becau...
Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Ba...
ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
13 years 11 months ago
The Molen FemtoJava Engine
This paper presents the Molen FemtoJava engine that is extended with concepts taken from the Molen polymorphic processor. This allows for the existing FemtoJava to be augmented wi...
Júlio C. B. de Mattos, Stephan Wong, Luigi ...