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ASAP
2006
IEEE
150views Hardware» more  ASAP 2006»
11 years 3 months ago
Architecture design of an H.264/AVC decoder for real-time FPGA implementation
This paper discusses hardware development of a realtime H.264/AVC video decoder. Synthesis results are presented for example implementations of the inverse quantization, inverse t...
Thomas Warsaw, Marcin Lukowiak
ASAP
2006
IEEE
116views Hardware» more  ASAP 2006»
11 years 3 months ago
Application Specific Processing: A Tools Approach
Drew Taussig, Andreas Hoffmann, Achim Nohl, Andrea...
ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
11 years 3 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy
ASAP
2006
IEEE
127views Hardware» more  ASAP 2006»
11 years 3 months ago
A Cost Effective Pipelined Divider for Double Precision Floating Point Number
Abstract--The growth of high-performance application in computer graphics, signal processing and scientific computing is a key driver for high performance, fixed latency, pipelined...
Sandeep B. Singh, Jayanta Biswas, S. K. Nandy
ASAP
2006
IEEE
119views Hardware» more  ASAP 2006»
11 years 3 months ago
From Bit Level Systolic Arrays to HDTV Processor Chips
The paper starts presents the work initially carried out by Queen's University and RSRE (now Qinetiq) in the development of advanced architectures and microchips based on sys...
John V. McCanny, Roger F. Woods, John G. McWhirter
ASAP
2006
IEEE
124views Hardware» more  ASAP 2006»
11 years 3 months ago
Low Complexity Design of High Speed Parallel Decision Feedback Equalizers
This paper proposes a novel parallel approach for pipelining of nested multiplexer loops to design high speed decision feedback equalizers (DFEs) based on look-ahead techniques. I...
Daesun Oh, Keshab K. Parhi
ASAP
2006
IEEE
134views Hardware» more  ASAP 2006»
11 years 3 months ago
Buffer and register allocation for memory space optimization
In today's embedded systems, memory hierarchy is rapidly becoming a major factor in terms of power, performance and area. This is especially true for embedded multimedia appl...
Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha...
ASAP
2006
IEEE
142views Hardware» more  ASAP 2006»
11 years 3 months ago
NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm
In this paper, a routing model for minimizing hot spots in the network on chip (NOC) is presented. The model makes use of AntNet routing algorithm which is based on Ant colony. Us...
Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kus...
ASAP
2006
IEEE
131views Hardware» more  ASAP 2006»
11 years 5 months ago
A Generic Multi-Phase On-Chip Traffic Generation Environment
We present hereafter a framework for on-chip traffic generation and networks-on-chip performance evaluation. This framework is based on a traffic generator that has three importan...
Antoine Scherrer, Antoine Fraboulet, Tanguy Risset
ASAP
2006
IEEE
114views Hardware» more  ASAP 2006»
11 years 5 months ago
The Mythical CCM: In Search of Usable (and Resuable) FPGA-Based General Computing Machines
Early FPGA researchers understood that FPGAs made possible the creation of a new, flexible, and powerful class of machine -- the configurable computing machine (CCM). The earliest...
Brent E. Nelson
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