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ASAP
2006
IEEE
106views Hardware» more  ASAP 2006»
13 years 11 months ago
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
13 years 11 months ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
ASAP
2006
IEEE
111views Hardware» more  ASAP 2006»
13 years 11 months ago
Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions
Current microprocessor instruction set architectures are word oriented, with some subword support. Many important applications, however, can realize substantial performance benefi...
Yedidya Hilewitz, Ruby B. Lee
ASAP
2006
IEEE
169views Hardware» more  ASAP 2006»
13 years 11 months ago
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing
Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a stat...
Hritam Dutta, Frank Hannig, Jürgen Teich, Ben...
ASAP
2006
IEEE
110views Hardware» more  ASAP 2006»
13 years 11 months ago
Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards
This paper proposes different low-cost coprocessors for public key authentication on 8-bit smart cards. Elliptic curve cryptography is used for its efficiency per bit of key and ...
Guerric Meurice de Dormale, Renaud Ambroise, David...
ASAP
2006
IEEE
109views Hardware» more  ASAP 2006»
13 years 11 months ago
Describing Quantum Circuits with Systolic Arrays
In the simulation of quantum circuits the matrices and vectors used to represent unitary operations and qubit states grow exponentially as the number of qubits increase. For insta...
Aasavari Bhave, Eurípides Montagne, Edgar G...
ASAP
2006
IEEE
110views Hardware» more  ASAP 2006»
13 years 11 months ago
Loop Transformation Methodologies for Array-Oriented Memory Management
Abstract – The storage requirements in data-dominant signal processing systems, whose behavior is described by arraybased, loop-organized algorithmic specifications, have an imp...
Florin Balasa, Per Gunnar Kjeldsberg, Martin Palko...
ASAP
2006
IEEE
85views Hardware» more  ASAP 2006»
13 years 11 months ago
High Speed Channel Coding Architectures for the Uncoordinated OR Channel
Herwin Chan, Miguel Griot, Andres I. Vila Casado, ...