Sciweavers

ASPDAC
2004
ACM
105views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Improved symbolic simulation by functional-space decomposition
Abstract — This paper presents a functional-space decomposition approach to enhance the capability of symbolic simulation. In our symbolic simulator, the control part and datapat...
Tao Feng, Li-C. Wang, Kwang-Ting Cheng
ASPDAC
2004
ACM
130views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Automatic process migration of datapath hard IP libraries
— While essential for high-performance circuit design, the custom nature of datapath components confines their use in only a few microprocessor companies. The reusability of dat...
Fang Fang, Jianwen Zhu
ASPDAC
2004
ACM
117views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Performance-driven global placement via adaptive network characterization
Delay minimization continues to be an important objective in the design of high-performance computing system. In this paper, we present an effective methodology to guide the delay...
Mongkol Ekpanyapong, Sung Kyu Lim
ASPDAC
2004
ACM
107views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Minimization of the expected path length in BDDs based on local changes
— In many verification tools methods for functional simulation based on reduced ordered Binary Decision Diagrams (BDDs) are used. The evaluation time for a BDD can be crucial an...
Rüdiger Ebendt, Wolfgang Günther, Rolf D...
ASPDAC
2004
ACM
98views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Enabling on-chip diversity through architectural communication design
- In this paper, we explore a new concept, called on-chip diversity, and introduce a design methodology for such emerging systems. Simply speaking, on-chip diversity means mixing d...
Tudor Dumitras, Sam Kerner, Radu Marculescu
ASPDAC
2004
ACM
119views Hardware» more  ASPDAC 2004»
13 years 10 months ago
A fast congestion estimator for routing with bounded detours
Congestion estimation is an important issue for the success of the VLSI layout. Fast congestion estimation provides an efficient means to adjust the placement and wire planning. A...
Lerong Cheng, Xiaoyu Song, Guowu Yang, Zhiwei Tang
ASPDAC
2004
ACM
85views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Buffer insertion is one...
Yi-Hui Cheng, Yao-Wen Chang