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ASPDAC
2004
ACM
92views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Modeling of coplanar waveguide for buffered clock tree
—Owing to inductive effect, coplanar waveguide (CPW) is widely used to achieve signal integrity in high performance clock designs. In this paper, we first propose a piece-wise l...
Jun Chen, Lei He
ASPDAC
2004
ACM
148views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Optimal planning for mesh-based power distribution
— Robust power distribution within available routing area resources is critical to chip performance and reliability. In this paper, we propose a novel and efficient method for o...
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ma...
ASPDAC
2004
ACM
80views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Exploiting program execution phases to trade power and performance for media workload
Abstract- Processing streaming media comprisesseveral program phases (often distinct) that are periodic and independent of application data. In this paper we characterize execution...
Subhasis Banerjee, G. Surendra, S. K. Nandy
ASPDAC
2004
ACM
96views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Register binding and port assignment for multiplexer optimization
- Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult pro...
Deming Chen, Jason Cong
ASPDAC
2004
ACM
71views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Golay and wavelet error control codes in VLSI
– This paper presents a high speed VLSI implementation of wavelet and golay error control codes. The design has been fabricated by MOSIS in a TSMC 0.25 µm CMOS process. Experime...
Arunkumar Balasundaram, Angelo Pereira, Jun-Cheol ...
ASPDAC
2004
ACM
107views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Interconnect capacitance estimation for FPGAs
Abstract—The dynamic power consumed by a digital CMOS circuit is directly proportional to capacitance. In this paper, we consider pre-routing capacitance estimation for FPGAs and...
Jason Helge Anderson, Farid N. Najm
ASPDAC
2004
ACM
141views Hardware» more  ASPDAC 2004»
13 years 10 months ago
An approach for reducing dynamic power consumption in synchronous sequential digital designs
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
Noureddine Chabini, Wayne Wolf
ASPDAC
2004
ACM
87views Hardware» more  ASPDAC 2004»
13 years 10 months ago
ShatterPB: symmetry-breaking for pseudo-Boolean formulas
Many important tasks in circuit design and verification can be performed in practice via reductions to Boolean Satisfiability (SAT), making SAT a fundamental EDA problem. However ...
Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Kare...
ASPDAC
2004
ACM
109views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Resource-constrained low-power bus encoding with crosstalk delay elimination
— In deep-submicron (DSM) technology, minimizing power consumption of a bus is one of the most important design objectives in embedded system-on-chip (SoC) design. In this paper,...
Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim
ASPDAC
2004
ACM
106views Hardware» more  ASPDAC 2004»
13 years 10 months ago
A novel memory size model for variable-mapping in system level design
— It is predicted that 70% of the chip area will be occupied by memories in future system-onchips. The minimization of on-chip memory hence becomes increasingly important for cos...
Lukai Cai, Haobo Yu, Daniel Gajski