block-based statistical timing

15

ASPDAC
2010
ACM

135views Hardware» more ASPDAC 2010»

Statistical timing verification for transparently latched circuits through structural graph traversal

13 years 3 months ago

Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...

Xingliang Yuan, Jia Wang

claim paper

Read More »

8

click to vote

TVLSI
2008

105views more TVLSI 2008»

Fast Estimation of Timing Yield Bounds for Process Variations

13 years 4 months ago

Download users.eecs.northwestern.edu

With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the "Max...

Ruiming Chen, Hai Zhou

claim paper

Read More »

10

click to vote

DAC
2004
ACM

94views Computer Architecture» more DAC 2004»

First-order incremental block-based statistical timing analysis

14 years 6 months ago

Download www.research.ibm.com

Chandramouli Visweswariah, K. Ravindran, K. Kalafa...

claim paper