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DATE
2000
IEEE
128views Hardware» more  DATE 2000»
11 years 6 months ago
A Bus Delay Reduction Technique Considering Crosstalk
As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays dominant part in wire load, crosstalk interference becomes a serious problem f...
Kei Hirose, Hiroto Yasuura
ISCAS
2005
IEEE
130views Hardware» more  ISCAS 2005»
11 years 7 months ago
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction
Inductance effects of on-chip interconnects have become more and more significant in today’s high-speed digital circuits, especially for global interconnects such as signal buse...
Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
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