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ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
9 years 5 months ago
Non-Inclusion Property in Multi-Level Caches Revisited
The center of gravity of computer architecture is moving toward memory systems. Barring breakthrough microarchitectural techniques to move processor performance to higher levels, ...
Mohamed M. Zahran, Kursad Albayraktaroglu, Manoj F...
IMS
2000
125views Hardware» more  IMS 2000»
9 years 9 months ago
Compiler-Directed Cache Line Size Adaptivity
The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size tha...
Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbau...
FPGA
2000
ACM
122views FPGA» more  FPGA 2000»
9 years 9 months ago
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
Huesung Kim, Arun K. Somani, Akhilesh Tyagi
MTDT
1999
IEEE
68views Hardware» more  MTDT 1999»
9 years 10 months ago
Unbalanced Cache Systems
The new concept of an unbalanced, hierarchicallydivided cache memory system is introduced and analyzed. This approach generalizes existing cache structures by allowing different m...
David L. Rhodes, Wayne Wolf
PARA
2004
Springer
9 years 11 months ago
Analyzing Advanced PDE Solvers Through Simulation
Abstract. By simulating a real computer it is possible to gain a detailed knowledge of the cache memory utilization of an application, e.g., a partial differential equation (PDE) s...
Henrik Johansson, Dan Wallin, Sverker Holmgren
ACMSE
2004
ACM
9 years 11 months ago
Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite
Replacement policy, one of the key factors determining the effectiveness of a cache, becomes even more important with latest technological trends toward highly associative caches....
Hussein Al-Zoubi, Aleksandar Milenkovic, Milena Mi...
ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
9 years 11 months ago
A non-uniform cache architecture for low power system design
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
Tohru Ishihara, Farzan Fallah
ISLPED
2006
ACM
109views Hardware» more  ISLPED 2006»
9 years 11 months ago
Power reduction of multiple disks using dynamic cache resizing and speed control
This paper presents an energy-conservation method for multiple disks and their cache memory. Our method periodically resizes the cache memory and controls the rotation speeds unde...
Le Cai, Yung-Hsiang Lu
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