Sciweavers

CAL
2006
13 years 4 months ago
A Case for Compressing Traces with BDDs
Instruction-level traces are widely used for program and hardware analysis. However, program traces for just a few seconds of execution are enormous, up to several terabytes in siz...
Graham D. Price, Manish Vachharajani
CAL
2006
13 years 4 months ago
Subtleties of Transactional Memory Atomicity Semantics
Abstract-- Transactional memory has great potential for simplifying multithreaded programming by allowing programmers to specify regions of the program that must appear to execute ...
Milo M. K. Martin, Colin Blundell, E. Lewis
CAL
2006
13 years 4 months ago
From sequential programs to concurrent threads
Chip multiprocessors are of increasing importance due to recent difficulties in achieving higher clock frequencies in uniprocessors, but their success depends on finding useful wor...
Guilherme Ottoni, Ram Rangan, Adam Stoler, Matthew...
CAL
2006
13 years 4 months ago
Adopting system call based address translation into user-level communication
User-level communication alleviates the software overhead of the communication subsystem by allowing applications to access the network interface directly. For that purpose, effici...
Moon-Sang Lee, Sang-Kwon Lee, Joonwon Lee, Seung R...
CAL
2006
13 years 4 months ago
User-Driven Frequency Scaling
Abstract-- We propose and evaluate User-Driven Frequency Scaling (UDFS) for improved power management on processors that support Dynamic Voltage and Frequency Scaling (DVFS), e.g, ...
Arindam Mallik, Bin Lin, Gokhan Memik, Peter A. Di...
CAL
2006
13 years 4 months ago
A Page-based Hybrid (Software-Hardware) Dynamic Memory Allocator
Modern programming languages often include complex mechanisms for dynamic memory allocation and garbage collection. These features drive the need for more efficient implementation ...
Wentong Li, Saraju P. Mohanty, Krishna M. Kavi
CAL
2006
13 years 4 months ago
An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation
Multiple core designs have become commonplace in the processor market, and are hence a major focus in modern computer architecture research. Thus, for both product development and ...
James Donald, Margaret Martonosi
CAL
2006
13 years 4 months ago
A case for fault tolerance and performance enhancement using chip multi-processors
This paper makes a case for using multi-core processors to simultaneously achieve transient-fault tolerance and performance enhancement. Our approach is extended from a recent late...
Huiyang Zhou
CAL
2006
13 years 4 months ago
Probabilistic counter updates for predictor hysteresis and bias
Hardware predictor designers have incorporated hysteresis and/or bias to achieve desired behavior by increasing the number of bits per counter. Some resulting proposed predictor de...
Nicholas Riley, Craig B. Zilles
CAL
2008
13 years 4 months ago
Pipelined Architecture for Multi-String Matching
We present a pipelined approach to hardware implementation of the Aho-Corasick (AC) algorithm for string matching called P-AC. By incorporating pipelined processing, the state grap...
Derek Chi-Wai Pao, Wei Lin, Bin Liu