Sciweavers

CAL
2008
13 years 4 months ago
Hierarchical Instruction Register Organization
This paper analyzes a range of architectures for efficient delivery of VLIW instructions for embedded media kernels. The analysis takes an efficient Filter Cache as a baseline and ...
David Black-Schaffer, James D. Balfour, William J....
CAL
2008
13 years 4 months ago
Randomized Partially-Minimal Routing on Three-Dimensional Mesh Networks
Abstract-- This letter presents a new oblivious routing algorithm for 3D mesh networks called Randomized PartiallyMinimal (RPM) routing that provably achieves optimal worstcase thr...
Rohit Sunkam Ramanujam, Bill Lin
CAL
2008
13 years 4 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny
CAL
2008
13 years 4 months ago
A Parallel Deadlock Detection Algorithm with O(1) Overall Run-time Complexity
This article proposes a novel parallel, hardware-oriented deadlock detection algorithm for multiprocessor system-on-chips. The proposed algorithm takes full advantage of hardware ...
Jaehwan John Lee, Xiang Xiao