Sciweavers

CAL
2007
13 years 4 months ago
Logic-Based Distributed Routing for NoCs
—The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. ...
José Flich, José Duato
CAL
2007
13 years 4 months ago
Probabilistic Prediction of Temporal Locality
—The increasing gap between processor and memory
Yoav Etsion, Dror G. Feitelson
CAL
2007
13 years 4 months ago
Dynamic Predication of Indirect Jumps
Abstract—Indirect jumps are used to implement increasinglycommon programming language constructs such as virtual function calls, switch-case statements, jump tables, and interfac...
José A. Joao, Onur Mutlu, Hyesoon Kim, Yale...
CAL
2007
13 years 4 months ago
A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed memory hierarchy enhancements for coher...
Jason Zebchuk, Andreas Moshovos
CAL
2007
13 years 4 months ago
Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy
Abstract—Some processors designed for consumer applications, such as Graphics Processing Units (GPUs) and the CELL processor, promise outstanding floating-point performance for ...
William R. Dieter, A. Kaveti, Henry G. Dietz
CAL
2007
13 years 4 months ago
Physical Register Reference Counting
—Several recently proposed techniques including CPR (Checkpoint Processing and Recovery) and NoSQ (No Store Queue) rely on reference counting to manage physical registers. Howeve...
A. Roth
CAL
2007
13 years 4 months ago
Corollaries to Amdahl's Law for Energy
—This paper studies the important interaction between parallelization and energy consumption in a parallelizable application. Given the ratio of serial and parallel portion in an...
Sangyeun Cho, Rami G. Melhem
CAL
2007
13 years 4 months ago
Microarchitectures for Managing Chip Revenues under Process Variations
—As transistor feature sizes continue to shrink into the sub-90nm range and beyond, the effects of process variations on critical path delay and chip yields have amplified. A com...
Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph...
CAL
2006
13 years 4 months ago
Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors
This paper evaluates asymmetric cluster chip multiprocessor (ACCMP) architectures as a mechanism to achieve the highest performance for a given power budget. ACCMPs execute serial ...
T. Y. Morad, Uri C. Weiser, A. Kolodnyt, Mateo Val...
CAL
2006
13 years 4 months ago
Performance modeling using Monte Carlo simulation
Abstract-- Cycle accurate simulation has long been the primary tool for micro-architecture design and evaluation. Though accurate, the slow speed often imposes constraints on the e...
Ram Srinivasan, Jeanine Cook, Olaf M. Lubeck