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ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
10 years 14 days ago
Pre-bond testable low-power clock tree design for 3D stacked ICs
Pre-bond testing of 3D stacked ICs involves testing individual dies before bonding. The overall yield of 3D ICs improves with prebond testability because designers can avoid stack...
Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung K...
ISLPED
2004
ACM
123views Hardware» more  ISLPED 2004»
10 years 8 months ago
Improved clock-gating through transparent pipelining
This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a ...
Hans M. Jacobson
DATE
2006
IEEE
176views Hardware» more  DATE 2006»
10 years 8 months ago
Low power synthesis of dynamic logic circuits using fine-grained clock gating
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Mei...
DAC
2003
ACM
11 years 3 months ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...
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