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ISLPED
2004
ACM

Improved clock-gating through transparent pipelining

13 years 9 months ago
Improved clock-gating through transparent pipelining
This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a significant amount of redundant clock pulses. The paper presents a new theory for optimal clocking of synchronous pipelines, presents practical implementations and evaluates the clock power benefits on a multiply/add-accumulate unit design. Transistor level simulations show that dynamic clock power dissipation can be reduced by 4060% at pipeline utilization factors between 20-60%, on top of traditional stage-level clock gating, without affecting pipeline latency or throughput. Categories and Subject Descriptors
Hans M. Jacobson
Added 30 Jun 2010
Updated 30 Jun 2010
Type Conference
Year 2004
Where ISLPED
Authors Hans M. Jacobson
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