Sciweavers

DLOG
2003
13 years 6 months ago
Applying Description Logic to Product Behavioral Design within Advanced CAD Systems
In this paper, we investigate the use of Description Logic (DL) for representing Product Behavioral constraints in Computer Aided Design (CAD) Systems. In an integrated design app...
François de Bertrand de Beuvron, Amadou Cou...
SEDE
2007
13 years 6 months ago
Case study: A tool centric approach for fault avoidance in microchip designs
— Achieving reliability in fault tolerant systems requires both avoidance and redundancy. This study focuses on avoidance as it pertains to the design of microchips. The lifecycl...
Clemente Izurieta
AGTIVE
2003
Springer
13 years 9 months ago
On Graphs in Conceptual Engineering Design
Abstract. This paper deals with knowledge-based computer aided design. A novel method giving additional support for conceptual design is presented. In this method, a designer firs...
Janusz Szuba, Agnieszka Ozimek, Andy Schürr
DATE
2006
IEEE
96views Hardware» more  DATE 2006»
13 years 10 months ago
On the relation between simulation-based and SAT-based diagnosis
The problem of diagnosis – or locating the source of an error or fault – occurs in several areas of Computer Aided Design, such as dynamic verification, property checking, eq...
Görschwin Fey, Sean Safarpour, Andreas G. Ven...
VLSID
2009
IEEE
144views VLSI» more  VLSID 2009»
14 years 5 months ago
Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications
The current paradigm of using Cu interconnects for on-chip global communication is rapidly becoming a serious performance bottleneck in ultra-deep submicron (UDSM) technologies. C...
Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi
VLSID
2009
IEEE
220views VLSI» more  VLSID 2009»
14 years 5 months ago
A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection
We propose a novel dependable SRAM with 7T cells and their array structure that avoids a half-selection problem. In addition, we introduce a new concept, "quality of a bit (Q...
Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi...
VLSID
2009
IEEE
139views VLSI» more  VLSID 2009»
14 years 5 months ago
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration
Increasing the number of cores in a multi-core processor reduces per-core performance. On the other hand, providing more resources to each core limits the number of cores on a chi...
Tameesh Suri, Aneesh Aggarwal
VLSID
2009
IEEE
107views VLSI» more  VLSID 2009»
14 years 5 months ago
Temperature Aware Scheduling for Embedded Processors
Power density has been increasing at an alarming rate in recent processor generations resulting in high on-chip temperature. Higher temperature results in poor reliability and inc...
Ramkumar Jayaseelan, Tulika Mitra
VLSID
2009
IEEE
141views VLSI» more  VLSID 2009»
14 years 5 months ago
A Comparison of Approaches to Carrier Generation for Zigbee Transceivers
Leburu Manojkumar, Arun Mohan, Nagendra Krishnapur...
VLSID
2009
IEEE
119views VLSI» more  VLSID 2009»
14 years 5 months ago
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems
Abstract-- Single-ended static random access memory (SESRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a ...
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhi...