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VLSID
2009
IEEE
108views VLSI» more  VLSID 2009»
14 years 5 months ago
Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems
Abstract--Digital control for embedded systems often requires low-power, hard real-time computation to satisfy high control-loop bandwidth, low latency, and low-power requirements....
Forrest Brewer, João Pedro Hespanha, Nitin ...
VLSID
2009
IEEE
115views VLSI» more  VLSID 2009»
14 years 5 months ago
Efficient Techniques for Directed Test Generation Using Incremental Satisfiability
Functional validation is a major bottleneck in the current SOC design methodology. While specification-based validation techniques have proposed several promising ideas, the time ...
Prabhat Mishra, Mingsong Chen
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
14 years 5 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
VLSID
2009
IEEE
143views VLSI» more  VLSID 2009»
14 years 5 months ago
SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems
Dynamic reconfiguration techniques are widely used for efficient system optimization. Dynamic cache reconfiguration is a promising approach for reducing energy consumption as well...
Weixun Wang, Prabhat Mishra, Ann Gordon-Ross
VLSID
2009
IEEE
130views VLSI» more  VLSID 2009»
14 years 5 months ago
Reversible Logic Synthesis with Output Permutation
Synthesis of reversible logic has become a very important research area. In recent years several algorithms ? heuristic as well as exact ones ? have been introduced in this area. ...
Daniel Große, Gerhard W. Dueck, Robert Wille...
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
14 years 5 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
VLSID
2009
IEEE
177views VLSI» more  VLSID 2009»
14 years 5 months ago
Accelerating System-Level Design Tasks Using Commodity Graphics Hardware: A Case Study
Many system-level design tasks (e.g. timing analysis, hardware/software partitioning and design space exploration) involve computational kernels that are intractable (usually NP-ha...
Unmesh D. Bordoloi, Samarjit Chakraborty
VLSID
2009
IEEE
150views VLSI» more  VLSID 2009»
14 years 5 months ago
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis...
VLSID
2009
IEEE
110views VLSI» more  VLSID 2009»
14 years 5 months ago
Security and Dependability of Embedded Systems: A Computer Architects' Perspective
Jörg Henkel, Roshan G. Ragel, Sri Parameswara...
VLSID
2009
IEEE
148views VLSI» more  VLSID 2009»
14 years 5 months ago
DFX and Productivity
Robert C. Aitken