Sciweavers

Share
CSREAESA
2006
10 years 23 hour ago
Java Flowpaths: Efficiently Generating Circuits for Embedded Systems from Java
The performance of software executed on a microprocessor is adversely affected by the basic fetchexecute cycle. A further performance penalty results from the load-execute-store p...
Darrin M. Hanna, Michael DuChene, Girma S. Tewolde...
CSREAESA
2006
10 years 23 hour ago
Reliable Management Services for COTS-based Space Systems and Applications
Hybrid spacecraft processing platforms that combine radiation-hardened components with commercialgrade COTS components have the potential to dramatically improve performance while ...
Ian A. Troxel, Eric Grobelny, Grzegorz Cieslewski,...
CSREAESA
2006
10 years 23 hour ago
Delay-Reduced Combinational Logic Synthesis using Multiplexers
- This paper presents an approach to obtain reduced hardware and/or delay for synthesizing logic functions using multiplexers. Replication of single control line multiplexer is use...
Rekha K. James, T. K. Shahana, K. Poulose Jacob, S...
CSREAESA
2006
10 years 23 hour ago
A Retargetable Compiler of VLIW ASIP for Media Signal Processing
Zhou Zhixiong, Yang Xu, He Hu 0002, Yihe Sun
CSREAESA
2006
10 years 23 hour ago
Generalized Deterministic Task Scheduling Algorithm for Embedded Real-Time Operating Systems
- In recent years, there has been a rapid and wide spread proliferation of non-traditional embedded computing platforms such as digital camcorders, cellular phones, and portable me...
Myoung-Jo Jung, Moon-Haeng Cho, Yong-Hee Kim, Cheo...
CSREAESA
2006
10 years 23 hour ago
Integration of an Analysis Tool for Large-Scale Embedded Real-Time Software into a Vehicle Control Platform Development Tool Cha
- We present a software tool for high-level design and analysis of large-scale embedded real-time software, which has been integrated into a vehicle control platform development to...
Xiaofeng Yin, Daniel L. Kiskis, Daniel Mihalik, Ka...
CSREAESA
2006
10 years 23 hour ago
Embedded Processor Based Built-In Self-Test and Diagnosis of Logic and Memory Resources in FPGAs
Abstract
Daniel T. Milton, Sachin Dhingra, Charles E. Strou...
CSREAESA
2006
10 years 23 hour ago
Power Optimization of Interconnection Networks for Transport Triggered Architecture
Transport triggered architecture (TTA) has been shown to provide an efficient way to design application specific instruction set processors. However, the interconnection network of...
Xue-mi Zhao, Zhiying Wang
CSREAESA
2006
10 years 23 hour ago
A Dual-core Embedded System-on-Chip Architecture for Multimedia Signal Processing Applications
- This paper presents a dual-core embedded System-on-Chip for a wide range of application fields with particularly high processing demands, including general signal processing, vid...
Hong Yue, Kui Dai, Zhiying Wang
books