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CSREAESA
2006

A Dual-core Embedded System-on-Chip Architecture for Multimedia Signal Processing Applications

8 years 11 months ago
A Dual-core Embedded System-on-Chip Architecture for Multimedia Signal Processing Applications
- This paper presents a dual-core embedded System-on-Chip for a wide range of application fields with particularly high processing demands, including general signal processing, video and audio processing, and a combination of these tasks. It integrates two processor cores and various interfaces onto a single chip, all tied to a 32-bit AMBA AHB bus. The RISC core coordinates the system and performs some reactive tasks, and the DSP core performs transformational tasks with more deterministic and regular behaviors, such as the small and well-defined workloads in multimedia signal processing applications. The DSP core is designed based on Transport Triggered Architecture (TTA) to reduce hardware complexity, get high flexibility and shorten market time. The processor is fabricated in 0.18um standard-cell technology, occupies about 9.7mm2 , and operates at 266MHz while consuming 670mW average power.
Hong Yue, Kui Dai, Zhiying Wang
Added 30 Oct 2010
Updated 30 Oct 2010
Type Conference
Year 2006
Where CSREAESA
Authors Hong Yue, Kui Dai, Zhiying Wang
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