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    DAC
    2007
    ACM
    149views Computer Architecture» more  DAC 2007»
    DDBDD: Delay-Driven BDD Synthesis for FPGAs
    14 years 5 months ago
    DDBDD: Delay-Driven BDD Synthesis for FPGAs
    Download  www.icims.csl.uiuc.edu
    Lei Cheng, Deming Chen, Martin D. F. Wong
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    DAC
    2007
    ACM
    115views Computer Architecture» more  DAC 2007»
    Layered Switching for Networks on Chip
    14 years 5 months ago
    Layered Switching for Networks on Chip
    Download  web.it.kth.se
    We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To s...
    Zhonghai Lu, Ming Liu, Axel Jantsch
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    DAC
    2007
    ACM
    131views Computer Architecture» more  DAC 2007»
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    14 years 5 months ago
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    Download  cobweb.ecn.purdue.edu
    This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
    Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
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    DAC
    2007
    ACM
    134views Computer Architecture» more  DAC 2007»
    Synthesizing Stochasticity in Biochemical Systems
    14 years 5 months ago
    Synthesizing Stochasticity in Biochemical Systems
    Download  www.paradise.caltech.edu
    Randomness is inherent to biochemistry: at each instant, the sequence of reactions that fires is a matter of chance. Some biological systems exploit such randomness, choosing betw...
    Brian Fett, Jehoshua Bruck, Marc D. Riedel
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    DAC
    2007
    ACM
    96views Computer Architecture» more  DAC 2007»
    Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits
    14 years 5 months ago
    Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits
    Download  www.eecg.toronto.edu
    Tomasz S. Czajkowski, Stephen Dean Brown
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    DAC
    2007
    ACM
    104views Computer Architecture» more  DAC 2007»
    Topology-Based Optimization of Maximal Sustainable Throughput in a Latency-Insensitive System
    14 years 5 months ago
    Topology-Based Optimization of Maximal Sustainable Throughput in a Latency-Insensitive System
    Download  www.cs.columbia.edu
    We consider the problem of optimizing the performance of a latency-insensitive system (LIS) where the addition of backpressure has caused throughput degradation. Previous works ha...
    Rebecca L. Collins, Luca P. Carloni
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    DAC
    2007
    ACM
    160views Computer Architecture» more  DAC 2007»
    Implicitly Parallel Programming Models for Thousand-Core Microprocessors
    14 years 5 months ago
    Implicitly Parallel Programming Models for Thousand-Core Microprocessors
    Download  impact.crhc.illinois.edu
    This paper argues for an implicitly parallel programming model for many-core microprocessors, and provides initial technical approaches towards this goal. In an implicitly paralle...
    Wen-mei W. Hwu, Shane Ryoo, Sain-Zee Ueng, John H....
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    DAC
    2007
    ACM
    135views Computer Architecture» more  DAC 2007»
    Novel CNTFET-based Reconfigurable Logic Gate Design
    14 years 5 months ago
    Novel CNTFET-based Reconfigurable Logic Gate Design
    Download  www.lirmm.fr
    This paper describes a family of novel dynamically reconfigurable logic gates based on double-gate carbon nanotube field-effect transistors which demonstrate p-type or n-type switc...
    David Navarro, Frédéric Gaffiot, Ian...
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    DAC
    2007
    ACM
    137views Computer Architecture» more  DAC 2007»
    Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting
    14 years 5 months ago
    Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting
    Download  www.ece.cmu.edu
    The number and magnitude of process variation sources are increasing as we scale further into the nano regime. Today's most successful response surface methods limit us to lo...
    Amith Singhee, Rob A. Rutenbar
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    DAC
    2007
    ACM
    126views Computer Architecture» more  DAC 2007»
    Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
    14 years 5 months ago
    Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
    Download  www.engr.uconn.edu
    Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
    Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
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