Sciweavers

DAC
2007
ACM
14 years 5 months ago
An Effective Guidance Strategy for Abstraction-Guided Simulation
tive Guidance Strategy for Abstraction-Guided Simulation Flavio M. De Paula Alan J. Hu Department of Computer Science, University of British Columbia, {depaulfm, ajh}@cs.ubc.ca D...
Flavio M. de Paula, Alan J. Hu
DAC
2007
ACM
14 years 5 months ago
Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits
Nishant Patil, Jie Deng, H.-S. Philip Wong, Subhas...
DAC
2007
ACM
14 years 5 months ago
Synchronous Elastic Circuits with Early Evaluation and Token Counterflow
A protocol for latency-insensitive design with early evaluation is presented. The protocol is based on a symmetric view of the system in which tokens carrying information move in ...
Jordi Cortadella, Michael Kishinevsky
DAC
2007
ACM
14 years 5 months ago
Self-Resetting Latches for Asynchronous Micro-Pipelines
Asynchronous circuits are increasingly attractive as low power or high-performance replacements to synchronous designs. A key part of these circuits are asynchronous micropipeline...
Tiberiu Chelcea, Girish Venkataramani, Seth Copen ...
DAC
2007
ACM
14 years 5 months ago
SODA: Sensitivity Based Optimization of Disk Architecture
Storage plays a pivotal role in the performance of many applications. Optimizing disk architectures is a design-time as well as a run-time issue and requires balancing between per...
Yan Zhang, Sudhanva Gurumurthi, Mircea R. Stan
DAC
2007
ACM
14 years 5 months ago
NBTI-Aware Synthesis of Digital Circuits
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
DAC
2007
ACM
14 years 5 months ago
Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors
Minimizing power consumption is vitally important in embedded system design; power consumption determines battery lifespan. Ultralow-power designs may even permit embedded systems...
Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert ...
DAC
2007
ACM
14 years 5 months ago
The Case for Low-Power Photonic Networks on Chip
Packet-switched networks on chip (NoC) have been advocated as a natural communication mechanism among the processing cores in future chip multiprocessors (CMP). However, electroni...
Assaf Shacham, Keren Bergman, Luca P. Carloni
DAC
2007
ACM
14 years 5 months ago
TROY: Track Router with Yield-driven Wire Planning
In this paper, we propose TROY, the first track router with yield-driven wire planning to optimize yield loss due to random defects. As the probability of failure (POF) computed f...
Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan
DAC
2007
ACM
14 years 5 months ago
Modeling the Function Cache for Worst-Case Execution Time Analysis
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...
Raimund Kirner, Martin Schoeberl