DATE
1997
IEEE
13 years 8 months ago
1997
IEEE
A new method for state justi cation is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is use...
DATE
1997
IEEE
13 years 8 months ago
1997
IEEE
In this paper a new approach is presented to build a list of faults to be used by the fault injection environment; the list is built starting from a high-level description of the ...
DATE
1997
IEEE
13 years 8 months ago
1997
IEEE
This paper presents a testability analysis and improvement technique for the controller of an RT level design. It detects hard-to-reachstates by analyzing both the data path and t...
DATE
1997
IEEE
13 years 8 months ago
1997
IEEE
In digital circuit simulation hidden opportunities for concurrent execution of models often exist, arising from the propagation delay associated with the generation of output even...
DATE
1997
IEEE
13 years 8 months ago
1997
IEEE
A structural, fault-model based methodology for the generation of compact high-quality test sets for analog macros is presented. Results are shown for an IVconverter macro design....
DATE
1997
IEEE
13 years 8 months ago
1997
IEEE
This paper describes a practical test approach for analog-to-digital converters (ADCs) based on the oscillation-test strategy. The oscillation-test is applied to convert the ADC u...
DATE
1997
IEEE
13 years 8 months ago
1997
IEEE
This paper proposes extensions to the VHDL grammar and de nes new semantics in the language to model the timing behavior of high frequency buses and clock lines with multiple, dis...
DATE
1997
IEEE
13 years 8 months ago
1997
IEEE
A design methodology for the synthesis of digital circuits used in high throughput digital modems is presented. The methodology spans digital modem design from the link level to t...
DATE
1997
IEEE
13 years 8 months ago
1997
IEEE
DATE
1997
IEEE
13 years 8 months ago
1997
IEEE
