DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
We extend the subsequence removal technique to provide signi cantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to ident...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
One of the main tasks within the high-level synthesis (HLS) process is the verification problem to prove automatically the correctness of the synthesis results. Currently, the res...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
Most memory test algorithms are optimized tests for a particular memory technology and a particular set of fault models, under the assumption that the memory is bit-oriented; i.e....
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
We present a new combinational verification technique where the functional specification of a circuit under verification is utilized to simplify the verification task. The main id...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of severa...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
Attribute grammars have been used extensively in every phase of traditional compiler construction. Recently, it has been shown that they can also be effectively adopted to handle ...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
1 Redundancy removal is an important step in combinational logic optimization. After a redundant wire is removed, other originally redundant wires may become irredundant, and some ...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
Partial Scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several ...