DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
Functional scan chains are scan chains that have scan paths through a circuit's functional logic and flip-flops. Establishing functional scan paths by test point insertion (T...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
Despite its importance, we find that a rigorous theoretical foundation for performing timing analysis has been lacking so far. As a result, we have initiated a research project th...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
We propose a new approach to RT-level power modeling for combinationalmacros, that does not require simulationbased characterization. A pattern-dependent power model for a macro i...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents a new approach to cross-level hierarchical high-level synthesis. A methodology is presented, that supports the efficient synthesis of hierarchical specified sy...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I...