DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
: Binary Decision Diagrams (BDDs) have been widely used in synthesis and verification. Boolean Satisfiability (SAT) Solvers, on the other hand, have been gaining
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
We present a framework that considers global routing, repeater insertion, and flip-flop relocation for early interconnect planning. We formulate the interconnect retiming and ...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
Execution time estimation of software at source-level is nowadays a crucial phase of the system design flow, especially for portable devices and real-time systems. From a source-...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
In this paper we present the results of a set of experiments we conducted in order to evaluate the viability of the behavioral synthesis, relying on the tools available at the mom...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
In this paper we present a microprocessor-based approach suitable for embedded flash memory testing in a System-on-achip (SOC) environment. The main novelty of the approach is the...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
We present a physical imrplementation of a 32-ports SPIN micro-network. For a 0.13 micron CMOS process, the total area is 4.6 ¢£¢¥¤ , for a cumulated bandwidth of about 100 G...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
We propose a new approach to accelerate transaction level verification by raising the productivity of the verification suites including test patterns, protocol checker, and simula...