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DATE
2005
IEEE
84views Hardware» more  DATE 2005»
13 years 10 months ago
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms
In this paper, we present a software compilation approach for microprocessor/FPGA platforms that partitions a software binary onto custom hardware implemented in the FPGA. Our app...
Greg Stitt, Frank Vahid
DATE
2005
IEEE
180views Hardware» more  DATE 2005»
13 years 10 months ago
A Coprocessor for Accelerating Visual Information Processing
Visual information processing will play an increasingly important role in future electronics systems. In many applications, e.g. video surveillance cameras, data throughput of mic...
Walter Stechele, L. Alvado Cárcel, Stephan ...
DATE
2005
IEEE
144views Hardware» more  DATE 2005»
13 years 10 months ago
Context Sensitive Performance Analysis of Automotive Applications
Accurate timing analysis is key to efficient embedded system synthesis and integration. While industrial control software systems are developed using graphical models, such as Ma...
Jan Staschulat, Rolf Ernst, Andreas Schulze, Fabia...
DATE
2005
IEEE
113views Hardware» more  DATE 2005»
13 years 10 months ago
Hardware-Software Design of a Smart Sensor for Fully-Electronic DNA Hybridization Detection
This paper describes the design of a smart sensor for label-free detection of DNA hybridization. The sensor is based on a direct electrical transduction principle: it measures imp...
Claudio Stagni, Carlotta Guiducci, Massimo Lanzoni...
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
13 years 10 months ago
Power Saving Techniques for Wireless LANs
Fast wireless access has rapidly become commonplace. Wireless access points and Hotspot servers are sprouting everywhere. Battery lifetime continues to be a critical issue in mobi...
Tajana Simunic
DATE
2005
IEEE
93views Hardware» more  DATE 2005»
13 years 10 months ago
A Faster Counterexample Minimization Algorithm Based on Refutation Analysis
It is a hot research topic to eliminate irrelevant variables from counterexample, to make it easier to be understood. The BFL algorithm is the most effective counterexample minimi...
ShengYu Shen, Ying Qin, Sikun Li
DATE
2005
IEEE
150views Hardware» more  DATE 2005»
13 years 10 months ago
Pueblo: A Modern Pseudo-Boolean SAT Solver
This paper introduces a new SAT solver that integrates logicbased reasoning and integer programming methods to systems of CNF and PB constraints. Its novel features include an eff...
Hossein M. Sheini, Karem A. Sakallah
DATE
2005
IEEE
112views Hardware» more  DATE 2005»
13 years 10 months ago
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in futu...
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinab...
DATE
2005
IEEE
107views Hardware» more  DATE 2005»
13 years 10 months ago
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prio...
Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chak...
DATE
2005
IEEE
105views Hardware» more  DATE 2005»
13 years 10 months ago
Mutation Sampling Technique for the Generation of Structural Test Data
Our goal is to produce validation data that can be used as an efficient (pre) test set for structural stuck-at faults. In this paper, we detail an original test-oriented mutation ...
Mathieu Scholivé, Vincent Beroulle, Chantal...