Sciweavers

DATE
2007
IEEE
79views Hardware» more  DATE 2007»
13 years 11 months ago
Utilization of SECDED for soft error and variation-induced defect tolerance in caches
Combination of SECDED with a redundancy technique can effectively tolerate a high variation-induced defect rate in future processes. However, while a defective cell in a block can...
Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima,...
DATE
2007
IEEE
134views Hardware» more  DATE 2007»
13 years 11 months ago
Non-fractional parallelism in LDPC decoder implementations
Because of its excellent bit-error-rate performance, the Low-Density Parity-Check (LDPC) decoding algorithm is gaining increased attention in communication standards and literatur...
John Dielissen, Andries Hekstra
DATE
2007
IEEE
73views Hardware» more  DATE 2007»
13 years 11 months ago
Design methods for security and trust
The design of ubiquitous and embedded computers focuses on cost factors such as area, power-consumption, and performance. Security and trust properties, on the other hand, are oft...
Ingrid Verbauwhede, Patrick Schaumont
DATE
2007
IEEE
79views Hardware» more  DATE 2007»
13 years 11 months ago
HW/SW implementation from abstract architecture models
plementation from Abstract Architecture Models Ahmed Amine Jerraya TIMA Laboratory - 46, av. Félix Viallet - 38031 Grenoble – France
Ahmed Amine Jerraya
DATE
2007
IEEE
106views Hardware» more  DATE 2007»
13 years 11 months ago
Optimized integration of test compression and sharing for SOC testing
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
DATE
2007
IEEE
133views Hardware» more  DATE 2007»
13 years 11 months ago
Stochastic modeling and optimization for robust power management in a partially observable system
As the hardware and software complexity grows, it is unlikely for the power management hardware/software to have a full observation of the entire system status. In this paper, we ...
Qinru Qiu, Ying Tan, Qing Wu
DATE
2007
IEEE
107views Hardware» more  DATE 2007»
13 years 11 months ago
Design of high-resolution MOSFET-only pipelined ADCs with digital calibration
Design of low-voltage high-resolution MOSFET-only pipeline analog to digital converters (ADCs) has been investigated in this work. The nonlinearity caused by replacing linear MIM ...
Hamed Aminzadeh, Mohammad Danaie, Reza Lotfi
DATE
2007
IEEE
138views Hardware» more  DATE 2007»
13 years 11 months ago
An ADC-BiST scheme using sequential code analysis
This paper presents a built-in self-test (BiST) scheme for analog to digital converters (ADC) based on a linear ramp generator and efficient output analysis. The proposed analysi...
Erdem Serkan Erdogan, Sule Ozev