Sciweavers

DATE
2007
IEEE
100views Hardware» more  DATE 2007»
14 years 3 months ago
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon W...
DATE
2007
IEEE
65views Hardware» more  DATE 2007»
14 years 3 months ago
Clock-frequency assignment for multiple clock domain systems-on-a-chip
Modern systems-on-a-chip platforms support multiple clock domains, in which different sub-circuits are driven by different clock signals. Although the frequency of each domain can...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
14 years 3 months ago
Double-via-driven standard cell library design
Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited ca...
Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Run...
DATE
2007
IEEE
83views Hardware» more  DATE 2007»
14 years 3 months ago
Temperature and voltage aware timing analysis: application to voltage drops
B. Lasbouygues, Robin Wilson, Nadine Azémar...
DATE
2007
IEEE
81views Hardware» more  DATE 2007»
14 years 3 months ago
Improving utilization of reconfigurable resources using two dimensional compaction
Partial reconfiguration allows parts of the reconfigurable chip area to be configured without affecting the rest of the chip. This allows placement of tasks at run time on the rec...
Ahmed A. El Farag, Hatem M. El-Boghdadi, Samir I. ...
DATE
2007
IEEE
76views Hardware» more  DATE 2007»
14 years 3 months ago
Heterogeneous systems on chip and systems in package
This paper discusses several forms of heterogeneity in systems on chip and systems in package. A means to distinguish the various forms of heterogeneity is given, with an estimati...
I. O'Connor, B. Courtois, K. Chakrabarty, N. Delor...
DATE
2007
IEEE
138views Hardware» more  DATE 2007»
14 years 3 months ago
Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling
—Increasing power density causes die overheating due to limited cooling capacity of the package. Conventional thermal management techniques e.g. logic shutdown, clock gating, fre...
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy