DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper we propose a hardware real time operating system (HW-RTOS) that implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified b...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Content addressable memory (CAM) is widely used in many applications that require fast table lookup. Due to the parallel comparison feature and high frequency of lookup, however, ...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
platform and a suite of abstract components with which new developments in different application domains can be engineered with minimal effort [1]p.16. Generic platforms, or refere...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Deep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware compo...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
We present a computationally efficient implementation of positive-real balanced truncation (PRBT) for symmetric multiple-input multiple-output (MIMO) systems. The solution of a p...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Wireless sensor networks operating on limited energy resources need to be power efficient to extend the system lifetime. This is especially challenging for video sensor networks d...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Moore’s Law will soon deliver tera-scale level transistor integration capacity. Power, variability, reliability, aging, and testing will pose as barriers and challenges to harne...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Several research activities have recently emerged aiming to propose multiprocessor implementations in order to achieve flexible and high throughput parallel iterative decoding. Be...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
: 2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive v...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...