DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
A vast literature has been published on Statistical Static Timing Analysis (SSTA), its motivations, its different implementations and their runtime/accuracy trade-offs. However, v...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Software implementations of modern block ciphers often require large lookup tables along with code size increasing optimizations like loop unrolling to reach peak performance on g...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Multiple asynchronous clock domains have been increasingly employed in System-on-Chip (SoC) designs for different I/O interfaces. Functional validation is one of the most expensiv...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in hi...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper we introduce a new algorithm for model order reduction in the presence of parameter or process variation. Our analysis is performed using a graph interpretation of t...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
In data dominated applications, loop transformations have a huge impact on the lifetime of array data and therefore on memory footprint. Since a locally optimal loop transformatio...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
The storage requirements of the array-dominated and looporganized algorithmic specifications running on embedded systems can be significant. Employing a data memory space much l...